In developing indie Semiconductor's next-generation ADAS processors, how do we optimize for real-time processing capabilities versus minimizing chip size and cost?

Introduction

The trade-off we're addressing is optimizing real-time processing capabilities versus minimizing chip size and cost for indie Semiconductor's next-generation ADAS processors. This scenario involves balancing performance with physical constraints and economic considerations. I'll analyze this trade-off by examining product requirements, stakeholder needs, and potential impacts, then propose a strategic approach to resolve it.

Step 1

Clarifying Questions (3 minutes)

• Context: I'm thinking this trade-off is driven by increasing demand for more advanced ADAS features. Could you confirm if this is primarily for Level 2+ autonomy or are we targeting higher levels?

Why it matters: Determines processing power requirements and cost sensitivity Expected answer: Level 2+ with roadmap to Level 3 Impact: Higher levels would prioritize performance over size/cost

• Business Context: Based on market trends, I assume our primary customers are Tier 1 automotive suppliers. Is this correct, and are we targeting any specific vehicle segments (e.g., luxury, mass-market)?

Why it matters: Influences price sensitivity and performance expectations Expected answer: Primarily Tier 1s, targeting mid to high-end vehicles Impact: Luxury focus would lean towards performance, mass-market towards cost

• User Impact: I'm thinking the end-users here are both drivers and OEMs. What specific ADAS features are most requested or expected in the next 2-3 years?

Why it matters: Helps prioritize processing capabilities Expected answer: Advanced emergency braking, adaptive cruise control, lane keeping Impact: More complex features would push towards higher performance

• Technical: Considering current semiconductor technology, what's our current node size, and what's the smallest we could feasibly go while maintaining yield?

Why it matters: Defines the range of our size optimization Expected answer: Currently at 14nm, could go to 7nm with acceptable yield Impact: Smaller nodes increase cost but allow for more processing power in same area

• Resource: Given the competitive nature of the semiconductor industry, I'm assuming we have a dedicated R&D team for this. What's our current capacity in terms of chip design and testing?

Why it matters: Determines our ability to iterate and optimize Expected answer: 50-person team with state-of-the-art simulation capabilities Impact: Larger team allows for more parallel optimization efforts